In the manufacture of integrated circuits each element is ordinarily produced by a lithographic process wherein an image of one or several of the individual circuit elements or features is projected onto the wafer at a time. Because of the small size of such elements and the importance of their being accurately sized and positioned, the fabrication equipment is frequently checked for a number of possible dimensional anomalies and aberrations.
A usual method at the present time for making such checks and measuring discrepancies is with a traditional box in a box configuration having an outside box of about 20 .mu.m square defined by a line or trench and a centrally disposed inside box of about 10 .mu.m square similarly defined by a line or trench. In either case the box in a box configuration utilizes measurements between edges of the two boxes.
In some instances, such as defined in the above identified parent application, it is useful to take calibrating measurements of lines that, when printed, are narrow enough to be shortened to the same degree that the feature lines of the finished circuit will be shortened. The degree of line shortening can then be determined and the dimensions of the mask feature can be accurately lengthened to compensate for the expected line shortening when the mask is used to create the line feature on the resist. In addition to lengthening the mask line, other forms of line shortening corrections may be used. Examples include the use of enlargements at the ends of the lines in the form of hammerheads or various other forms of serifs. Very small island features (also known as pillar features) have the same shortening effect as narrow lines, but in two dimensions rather than one. Many of the same forms of correction used to correct line shortening can also be used to correct the shortening of both dimensions of islands.
In all cases it is important to recognize the capability of the overlay metrology tool and its need to recognize the edges of the two boxes. To provide this recognition, each of the two boxes must present a color shading discernibly different from the other so that their line of junction can be recognized. When one of the boxes is formed as a solid square rather than merely a line configuration, target acquisition by the metrology tool used to measure misalignment is facilitated.
Thus, if the outside box is formed of a solid sheet of chrome on glass and the inside box is formed by removing a square of the chrome to provide a view of clear glass, the difference in the color shading is at a maximum and the metrology machine can easily detect the juncture of the two. On the other hand, if one of the boxes is formed as a pattern of laterally spaced lines extending in the horizontal direction and the other of laterally spaced lines extending in the vertical direction, they will both exhibit the same color shading and therefore make target acquisition a very difficult task for the metrology tool. Furthermore, in making measurements, the metrology tool most easily recognizes various measurement points when the shading differences on each side of the various junctions are all substantially the same. Thus, if at one measurement point the shading on one side of the junction is much darker than the shading on the other side, the tool will seek junctions having the same difference of shading on the two sides.
In many instances, the individual features of a circuit, such as the gate lines, have extremely small dimensions and may have widths of less than 0.2 .mu.m to 0.4 .mu.m with their lengths being considerably greater, perhaps 0.8 .mu.m to 2.0 .mu.m. Moreover, the thin gate lines may well be intended for connection to other layers of the integrated circuit by way of narrow vias filled with electrically conductive material. When dimensions reach such small size there is not only a tendency for the formed line to be shorter than its design length as defined by the mask, but also the positioning of the vias may be misplaced sufficiently to cause less than adequate registration with the narrow gate line. Such critical dimension transfer difference occurs when a desired circuit feature is particularly thin or small because the light passed through the mask onto the resist to define the feature is refracted in the resist itself. With large features, the refracted light is relatively minor compared to the overall size of the feature. However, as the size of the feature diminishes that same degree of refraction impinges upon a larger percentage of the feature area. The effect of such refraction is increased when the projection is out of focus, thereby causing even more light scatter.